1. Field of the Invention
This invention relates in general to 3-D integration of circuits and more specifically to a barrier for use in 3-D integration of circuits.
2. Description of the Related Art
Traditionally, 3-D integration of circuits is achieved using face-to-face bonding of wafers, such as acceptor wafers and donor wafers, or dies. Acceptor wafer is typically the bottom wafer and donor wafer is typically the top wafer. Interconnects in the bonded wafers or dies are connected using various techniques, such as stitch vias. Formation of stitch vias, which are typically formed on the backside of a donor wafer, is, however, time consuming and requires additional steps for achieving 3-D integration of wafers or dies. In particular, for example, formation of stitch vias requires two inter-wafer vias having differing lengths that are linked on the backside of the donor wafer.
Additionally, etching of inter-wafer vias can cause several problems for etch processing. For example, etching of such inter-wafer vias in low-K dielectric wafers requires etching through multiple types of dielectric materials, such as silicon nitride, silicon carbon-nitride, silicon-oxide, and SiCOH containing low-K dielectrics. This in turn requires a wide range of etch processes, such as both physical and chemical etch processes. Certain physical and chemical etch processes can redistribute the copper into the dielectric layers. This problem, for example, especially occurs when inter-wafer connects are used as embedded etch masks.
Thus, there is a need for improved 3-D integration of circuits.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.